1. Field of the Invention
This invention pertains to a tunneling transistor and in particular to an interband lateral resonant tunneling transistor.
2. Description of Related Art
Conventional semiconductor technologies are rapidly approaching practical limits to minimum device sizes which can be achieved in very large scale integrated (VLSI) circuits. It is estimated that the limit of the minimum active-region dimension, L (gate length, channel length, etc.), of such devices are on the order of 1000 .ANG. for both bipolar and field effect transistor (FET) devices. Conventional device speeds are similarly limited, since there is a direct correlation between size and speed and the maximum cutoff frequencies achievable are estimated to be in the order of 300 GHz. At the present rate of development, these limits will have been reached by around the turn of the century.
In order to achieve the ultimate limits in downscaling, Randall et al. in the paper Nanoelectronics: Fanciful physics or real devices?, J. Vac. Sci. Technol., B7(6), pp. 1398-1404, Nov./Dec. 1989, discussed heterojunction technology employed to form tunneling barriers and quantum wells. The tunnel barrier is a thin slab of wide band gap material clad by a narrow band gap material. When the layer is physically thin enough, (comparable to the electron wavelengths) quantum mechanical tunneling through the barrier is permitted. The quantum well is complementary to the tunnel barrier. It is a slab of sufficiently thin narrow band gap material surrounded by a wide band gap material. Electrons confined to this layer will have quantized energy levels where the ground state energy is higher than the conduction band edge found in a bulk crystal.
A transistor utilizing resonant tunneling (RT) diode technology, where tunnel barriers and quantum wells are combined to form a quantum effect device, has been proposed as one means to overcome the problems foreseen in VLSI technology. This proposal is based upon the extremely high speed associated with tunneling phenomena, and in part on the small minimum intrinsic length which is required (present vertical diodes are often less than 100 .ANG. thick). It is advantageous to reduce both the longitudinal and lateral dimensions of an RT diode or transistor, because this sharpens the quantum resonances.
The resonant tunneling (RT) diode technology has been around for the past two decades and one popular approach is to put a double-barrier quantum well structure inside a bipolar transistor or in series with a modulation-doped field-effect transistor (MODFET) having a single gate structure. Nearly all resonant tunneling transistor devices reported to date have employed vertical geometry.
Another approach is shown in FIG. 1 where the lateral resonant tunneling field-effect transistor (LARTFET) 10, which is very similar to the MODFET, except that it has dual closely spaced nanometer gates 12 and 14. The dual gates, or electrodes,12, 14 electrostatically create double potential barriers in the channel and a quantum well 16 in between. By controlling the potential on the gates, 12 and 14, the barrier heights, 18 and 22, can be adjusted continuously. This technology is set forth in the paper by Chou etal., Observation of electron resonant tunneling in a lateral dual-gate resonant tunneling field-effect transistor, Appl. Phys. Lett. 55 (2), pp. 176-178, Jul. 1989. A similar technology having two or three closely separated, independently controlled gate fingers, termed a planar resonant tunneling field-effect transistor (PRESTFET), has been reported by Ismail etal. in the paper entitled Lateral Resonant tunneling in a double-barrier field-effect transistor, Appl. Phys. Lett. 55(6), pp. 589-591, Aug. 1989. In the devices reported by both Chou et al. and Ismail et al., potentials applied to the dual gates (separated from the GaAs channel by an Al.sub.x Ga.sub.1-x layer) induce barriers that quantize the electron states in the central region. In both papers, the quantum well width, L.sub.W and gate length, L.sub.G, are in the 600-1000 .ANG. range. Also see, U.S. Pat. No. 5,241,190, Eisenstein et al. which describes a resonant tunneling transistor having a plurality of gates disposed on opposing sides of the transistor structure.
Therefore, while lateral structures have considerable architectural advantages in ultra-dense circuits, the lateral tunneling transistors presently available to the art have displayed negative differential resistance only at extremely low temperatures (4.2K). Most of these have displayed either low transconductance or low impedance, which accounts in part for the fact that demonstrated circuits have generally employed no more than a single transistor.
This is because the transconductance, g.sub.m, is far too small to be useful in driving other devices. Although vertical RT devices can in principle be reduced to a size much smaller than the 1000 .ANG. limit for conventional transistors, fabrication becomes increasingly difficult because of the need to individually contact the three different vertical layers.
It is well known that semiconductors with small energy gaps have small effective masses as well, and hence far greater response to quantum phenomena than do wide gap semiconductors confined to the same scale length. Quantum-effect devices will therefore operate at much higher temperatures, and processes which are too weak to be useful in wide-gap configurations become practical when a narrow-gap nanostrucure is employed. Also, depletion of the carrier population becomes a serious limitation in wide-gap nanostructure devices with the shrinking of the device size due to the pinning of the Fermi level by mid-gap states.
Quantum wells produce confinement in one dimension only. When one lateral dimension is reduced a quantum wire is obtained. When both lateral dimensions are reduced to the order of the electron wavelength, the bands are split into discrete electron states and one obtains a "quantum dot."